This invention relates to a semiconductor device and a method of manufacturing the same.
An insulating gate type transistor (thereinafter, abbreviated as a MOSFET) for high breakdown voltage specification has generally a drain diffusion layer. In this event, the drain diffusion layer has a relatively low concentration and a long dimension (length) in a current direction. Herein, it is to be noted that the drain diffusion layer having such a structure will be thereinafter called an extended drain diffusion layer.
In this case, when the extended drain diffusion layer has high concentration, an on-resistance is reduced and conversely, a breakdown voltage between a drain region and a source region is lowered. This fact is true with respect to length of the extended drain diffusion layer in the current direction. Thus, there is a trade-off relationship between the breakdown voltage (between the source region and the drain region) and the on-resistance.
It is important in development of a device having a large power and a high breakdown voltage to realize a smaller on-resistance with the same breakdown voltage under a desired area occupied on a chip.
Various suggestions have been so far made to reduce the on-resistance.
One suggestion has been made about a MOSFET, which has a diffusion layer opposite to the extended drain diffusion layer. For instance, disclosure has been made about the MOSFET in which a diffusion layer having a reverse conductive type (thereinafter, referred to as a reverse conductive type diffusion layer) is formed in the extended drain diffusion layer, and the diffusion layer is set to the same potential with the source region in NEC Res.and Develop. Vol.35, No.4, October 1994 (thereinafter, called a first conventional reference).
Further, disclosure has been made about a MOS FET in which the above-mentioned reverse conductive type diffusion layer is put into an open state in Japanese Unexamined Patent Publication (JP-A) No. Sho. 55-108773 (thereinafter, called a second conventional reference). Such a MOS transistor has an excellent characteristic between a rated voltage and an on-resistance.
Moreover, the other various conventional techniques related to this invention have been known. For instance, disclosure has been made about xe2x80x9ca lateral type field effect transistor having high breakdown voltage and a method of manufacturing the samexe2x80x9d for improving the trade-off relationship between the breakdown voltage and the on-resistance of a lateral type MOSFET integrated in a power IC in Japanese Unexamined Patent Publication (JP-A) No. Hei. 8-107202 (thereinafter, called a third conventional reference). In the third conventional reference, a P-well region is formed on a surface layer of a p-type substrate, and an N-drain region including an N-offset region having a LOCOS layer is formed on the surface layer. Thus, the MOSFETS are structured according to the above disclosures.
However, the third conventional reference does not disclose the reverse conductive type diffusion layer at all, and is also different from structure of this invention.
In addition, disclosure has been made about a structure of a MOSFET, which has a high breakdown voltage and occupies a narrower area in comparison with the conventional structure in Japanese Unexamined Patent Publication (JP-A) No. Hei. 8-255913 (thereinafter, called a fourth conventional reference).
In the fourth conventional reference, a highly doped drain region is formed by doping substance of silicon via an opening portion of a field oxide film to save a silicon area and reduce an inherent resistance PDOSon. In this event, the field oxide film is obtained by the known selective/anisotropy etching using a strip of a polysilicon which serves as a gate electrode and a field electrode as a mask.
However, the fourth conventional reference does not disclose the reverse conductive type diffusion layer at all, and also is different from the structure of this invention, like the third conventional reference.
Further, description has been made about a high voltage RESURF EDMOS transistor having bi-directional characteristic in Japanese Unexamined Patent Publication (JP-A) No. Hei 9-186242 (thereinafter, referred to as a fifth conventional reference). The fifth conventional reference can be mainly applied for a multiplexer having three inputs or more.
However, the fifth conventional reference does not disclose the reverse conductive type diffusion layer at all, and is also different from the structure of this invention, like the third conventional reference.
In the above-mentioned conventional references, the MOSFET inevitably has variation regarding electrical characteristic for reasons related to manufacturing process.
In the meanwhile, a pixel emits under high electrical field in a display which utilizes an electro-luminesance (EL) and a plasma display panel (PDP). Therefore, a scanning line electrode or a date line electrode has capacitance. Specifically, each of these electrodes has capacitance of several nF/line. This means that large capacitance is repeatedly and electrically charged and discharged. To this end, electric power is recovered during the discharge to suppress consumption power.
In such a recovering system, a diode is connected to an output terminal of a driving device. The electrical power is recovered from a forward direction current, which flows along the diode. It is required that the diode has considerably small resistance to recover the electric power. In addition, the diodes are required twice for the number of the electrodes.
Further, it is necessary that the diode is formed in a small-occupied area on the same chip as a semiconductor integrated circuit for driving so as to restrain manufacturing cost.
At the same time, the diode generally has a buried epitaxial structure and an insulator-separating structure formed by a complicated manufacturing process to prevent reduction of the electric power recovering efficiency due to an effect of a parasitic bipolar device during recovering the electric power.
It is therefore an object of this invention to provide a semiconductor device, which is capable o f suppressing variation of electrical characteristic and a method of manufacturing the same.
It is another object of this invention to provide a semiconductor device, which is suitable for miniaturization and a method of manufacturing the same.
It is still other object of this invention to provide a semiconductor device, which is capable of reducing operation resistance of a diode between a drain region and a source region and a method of manufacturing the same.
It is still other object of this invention to provide a semiconductor device which is capable of taking out a wire line from a reverse conductive type diffusion layer in an extended drain diffusion layer and using it as a independent terminal.
It is still other object of this invention to provide a semiconductor device, which is capable of reducing common-emitter direct current amplification factor and a method of manufacturing the same.
It is still other object of invention to provide a semiconductor device which has large degree of freedom of an electrode wiring pattern and a method of manufacturing the same.
It is still other object of this invention to provide a semiconductor device which has excellent reliability and yield and a method of manufacturing the same.
It is still other object of this invention to provide a driving device using the above-mentioned semiconductor device.
In a semiconductor device according to this invention, a source diffusion layer is formed in a substrate. Further, a drain extended diffusion layer is formed in the substrate. A drain diffusion layer is formed in the extended drain diffusion layer.
In this condition, a reverse conductive type diffusion layer is formed adjacent to the drain diffusion layer in the extended drain diffusion layer. In this event, the reverse conductive type diffusion layer has a conductive type opposite to that of the extended drain diffusion layer.
With such a structure, a main gate region is formed between the source diffusion layer and the drain extended diffusion layer and on the substrate. Moreover, a sub-gate region is formed between the reverse conductive type diffusion layer and the drain diffusion layer and on the extended drain diffusion layer.
In this case, the main gate region is composed of a main gate oxide film and a main gate electrode formed thereon while said sub-gate region is composed of a sub-gate oxide film and a sub-gate electrode formed thereon.
Further, a source electrode is placed on the source diffusion layer while a drain electrode is placed on the drain diffusion layer. Herein, the drain electrode contacts with the sub-gate electrode.
In addition, a terminal electrode is placed on the reverse type conductive layer. In this event, the terminal electrode is used as an independent terminal.